This invention is in the field of integrated circuits. Embodiments of this invention are more specifically directed to solid-state static random access memories (SRAMs), and power reduction in those SRAMs.
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. Many of these electronic devices and systems are now handheld portable devices. For example, many mobile devices with significant computational capability are now available in the market, including modern mobile telephone handsets such as those commonly referred to as “smartphones”, personal digital assistants (PDAs), mobile Internet devices, tablet-based personal computers, handheld scanners and data collectors, personal navigation devices, and the like. Of course, these systems and devices are battery powered in order to be mobile or handheld. The power consumption of the electronic circuitry in those devices and systems is therefore of great concern, as battery life is often a significant factor in the buying decision as well as in the utility of the device or system.
The computational power of these modern devices and systems is typically provided by one or more processor “cores”, which operate as a digital computer in carrying out its functions. As such, these processor cores generally retrieve executable instructions from memory, perform arithmetic and logical operations on digital data that are also retrieved from memory, and store the results of those operations in memory; other input and output functions for acquiring and outputting the data processed by the processor cores are of course also provided. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems.
Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in these modern power-conscious electronic systems. As is fundamental in the art, SRAM memory cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data are stored as charge on solid-state capacitors, and must be periodically refreshed in order to be retained.
Advances in semiconductor technology in recent years have enabled shrinking of minimum device feature sizes (e.g., MOS transistor gates) into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. As a result, significant memory resources are now often integrated as embedded memory into larger-scale integrated circuits, such as microprocessors, digital signal processors, and “system-on-a-chip” integrated circuits. However, this physical scaling of device sizes raises significant issues in connection with such embedded memory.
One such problem is the substantial DC current due to sub-threshold leakage and other short channel effects of the transistors in SRAM cells, resulting in increased DC data retention current drawn by embedded memory arrays. Designers have recently adopted circuit-based approaches for reducing power consumed by integrated circuits including large memory arrays. One common approach is to reduce the power supply voltage applied to memory arrays, relative to the power supply voltage applied to logic circuitry and circuitry peripheral to the memory array (e.g., decoders, sense amplifiers, etc.). This approach not only reduces the power consumed by the memory array, but also helps to reduce sub-threshold leakage in the individual cells.
Another circuit-based approach to reducing power consumption involves placing the memory functions within the integrated circuit into a retention state when possible. In conventional memory retention states, the power supply voltages applied to the memory array are reduced to voltages below that necessary for access, but above the minimum required for data states to be retained in the memory cells (i.e., above the data-state retention voltage, or “DRV”); memory peripheral circuits are also powered down in this full retention mode, saving additional power. Typically, the “Vdd” power supply voltage applied to the loads of SRAM cells (e.g., the source nodes of the p-channel transistors in CMOS SRAM cells) is reduced in this retention mode; well bias voltages may also be modulated in this retention mode, for example to increase transistor threshold voltages and thus further reduce device leakage. However, significant recovery time is typically involved in biasing the memory array to an operational state from the retention state.
Recently, an intermediate power-down mode has been implemented in integrated circuits with memory arrays of significant size. This intermediate mode is referred to in the art as “retain-till-accessed”, or “RTA”, and is most often used in those situations in which the memory arrays are split into multiple blocks. In the RTA mode, the peripheral memory circuitry remains fully powered and operational. However, only those block or blocks of the memory array that are being accessed are fully powered; other blocks of the memory that are not being accessed are biased to a reduced array power supply voltage (i.e., above the retention voltage) to reduce power consumption while idle. Well and junction biases (i.e., other than the bias of p-channel MOS source nodes that receive the reduced RTA bias) are typically maintained at the same voltages in RTA mode as in read/write operation, to reduce the recovery time from RTA mode. The power saving provided by the RTA mode can be substantial, especially if some of the larger memory blocks are accessed infrequently. Because of its ability to be applied to individual blocks within a larger-scale integrated circuit, as well as its fast recovery time, the RTA standby mode is now often used with embedded memories in modern mobile Internet devices and smartphones, considering that these devices remain powered-on but not fully active for much of their useful life.
From a circuit standpoint, integrated circuit memories having an RTA mode must include circuitry that establishes the reduced RTA array bias voltage, and that switchably controls entry into and exit from RTA mode during operation. FIG. 1a is a block diagram of a conventional integrated circuit 2 in which such RTA standby is provided. Integrated circuit 2 includes memory array 5, arranged into multiple memory array blocks 60 through 63 of different sizes relative to one another. Each memory array block 6 is associated with corresponding decode and read/write circuitry 11 that addresses, writes data to, and reads data from its associated memory array block 6. Integrated circuit 2 also includes functional and power management circuitry 4, which includes the logic functionality provided by integrated circuit 2, and also circuitry for regulating and distributing power supply voltages throughout integrated circuit 2. For purposes of this example of memory array 5, functional and power management circuitry 4 produces a voltage on power supply line Vddm that is sufficient for memory read and write operations. Functional and power management circuitry 4 also produces a “periphery” power supply voltage on power supply line VddP, which is applied to decoder and read/write circuitry 11 and is typically at a different voltage from that of the power supply voltage on line Vddm applied to memory array 5 during reads and writes, as known in the art. The actual array power supply voltage applied to each memory array block 60 through 63 is presented on power supply lines VddAR0 through VddAR3, respectively. The voltages on lines VddAR0 through VddAR3 are defined by way of bias/switch circuits 70 through 73, respectively, and based on the voltage at power supply line Vddm, as will be described below.
Each memory array block 6 in this conventional integrated circuit 2 is constructed as an array of SRAM cells arranged in rows and columns. As shown in FIG. 1b by the example of six-transistor (6-T) memory cell 12j,k, which is in the jth row and kth column of one of memory array blocks 6, each SRAM memory cell 12 is biased between the voltage on power supply line VddAR and a reference voltage (e.g., at ground reference Vss). SRAM memory cell 12j,k in this case is constructed in the conventional manner as a pair of cross-coupled CMOS inverters, one inverter of series-connected p-channel transistor 13p and n-channel transistor 13n with their drains at node S1, and the other inverter of series-connected p-channel transistor 14p and n-channel transistor 14n with their drains at node S2; the gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter, in the usual manner. N-channel pass transistors 15a, 15b have their source/drain paths connected between respective cross-coupled nodes S1, S2 and a corresponding one of complementary bit lines BLk, BL*k, respectively; the gates of pass transistors 15a, 15b are driven by word line WLj for the row. Accordingly, as known in the art, DC current drawn by SRAM cell 12j,k amounts to the sum of the off-state source/drain leakage currents through one of p-channel transistors 13p, 14p and one of n-channel transistors 13n, 14n, plus any gate oxide leakage that may be present. As mentioned above, if transistors 13, 14 are extremely small sub-micron devices, these leakage currents can be significant (as much as 1 nA per memory cell), and can thus result in significant overall standby power consumption if the number of memory cells 12 in memory array blocks 6 is large.
Referring back to FIG. 1a, memory array blocks 60 through 63 may be independently biased into RTA mode in this conventional integrated circuit 2, by operation of bias/switch circuits 70 through 73, respectively. The construction of bias/switch circuit 71 is illustrated in FIG. 1a by way of example. P-channel transistor 8 is connected in diode fashion, with its source at power supply line Vddm and its drain and gate connected to node VddAR1; the voltage drop across transistor 8 from the voltage at line Vddm thus establishes voltage on power supply line VddAR1. In some cases, transistor 8 is realized as an n-channel MOS transistor connected in diode fashion. Shorting transistor 9 is a relatively large p-channel power transistor with its source/drain path connected between power supply line Vddm and power supply line VddAR1, and its gate receiving control signal RTA1 from functional and power management circuitry 4. If memory array block 61 is being accessed for a read or write operation, control signal RTA1 is driven to a low logic level, which turns on transistor 9 in bias/switch circuit 71 and shorts out diode 8, setting the voltage at line VddAR1 at that of power supply line Vddm. Conversely, if memory array block 61 is to be placed in RTA mode, functional and power management circuitry 4 will drive control signal RTA1 to a high logic level. This turns off transistor 9 in bias/switch circuit 71, such that the voltage drop across diode 8 establishes the voltage at node VddAR1 at a lower voltage (by one diode drop) than the voltage at power supply line Vddm. In this RTA mode, therefore, the power consumed by memory array block 61 will be reduced by an amount corresponding to at least the square of this voltage reduction. Meanwhile in this RTA mode, periphery power supply line VddP applied to peripheral memory circuitry, such as decoder and read/write circuitry 11 for each memory array block 6, carries its normal operating voltage, so that this peripheral circuitry is ready to perform an access of its associated memory array block.
A second problem encountered in connection with embedded SRAM memory now realized by modern manufacturing technology stems from the increased variability in the electrical characteristics of transistors formed at these extremely small feature sizes. This variability in characteristics has been observed to increase the likelihood of read and write functional failures, on a cell-to-cell basis. The combination of increased device variability with the larger number of memory cells (and thus transistors) within an integrated circuit renders a higher likelihood that one or more cells cannot be read or written as expected.
A particular failure mode that has been observed in conventional modern SRAM memories is the failure to switch the state of an SRAM cell in a write operation. Typically, this failure has been observed to be due to the inability of write circuitry to pull down the sense node currently latched to a high voltage. Referring to SRAM cell 12j,k of FIG. 1b, consider the case in which node S1 is at a high level and node S2 is at a low level, with word line WLj turned off. In order to write the opposite state into SRAM cell 12j,k, write circuitry operates to pull down bit line BLk toward Vss while word line WLj is turned on. If device imbalances within SRAM cell 12j,k render the write circuitry incapable of “flipping” the state of SRAM cell 12j,k in this manner, the write operation will fail and node S1 will remain latched at a high level despite the attempted write operation.
A circuit-based approach to reducing the likelihood of write failures in modern SRAM memories is referred to in the art as “write assist”. FIG. 1c illustrates one example of conventional write assist circuitry in an SRAM memory. In FIG. 1c, 6-T SRAM cells 12 in two columns k, k+1, and three rows j, j+1, j+2 in memory array block 6m are shown by way of example; it will be understood, of course, that many more rows and columns of SRAM cells 12 will typically be present in a given memory array block. SRAM cells 12 in the same row share the same word line (e.g., SRAM cells 12j,k and 12j,k+1 each receive word line WLj), and SRAM cells in the same column are coupled to the same bit line pair (e.g., SRAM cells 12j,k, 12j+1,k, 12J+2,k are each connected to bit lines BLk, BL*k). For purposes of write assist, columns k, k+1 are associated with a write assist transistor 17k, 17k+1, respectively. In this conventional arrangement, the number of write assist transistors 17 equals the number of columns of SRAM cells 12. Each write assist transistor 17k, 17k+1 is constructed as a p-channel MOS (i.e., PMOS) transistor, each with its source connected to power supply node Vdd. Write assist transistor 17k has its drain connected to power supply line Vddm[k], which provides the “Vdd” bias to each of SRAM cells 12 in column k; similarly, write assist transistor 17k+1 has its drain connected to power supply line Vddm[k+1], which biases SRAM cells in column k+1. As such, separate Vdd bias is provided to each column of SRAM cells 12 in this arrangement. The gate of write assist transistor 17k receives write control signal WR[k], and the gate of write assist transistor 17k+1 receives write control signal WR[k+1].
This conventional write assist approach operates to float the Vdd bias to SRAM cells 12 in columns that are being written. More specifically, with reference to FIG. 1c, write control signals WR[k], WR[k+1] remain inactive low during read cycles, standby periods, or write operations to other columns. Write assist transistors 17k, 17k+1 remain turned on by write control signals WR[k], WR[k+1] remaining inactive low during these times, allowing each of SRAM cells 12 in columns k, k+1 to be biased from power supply node Vdd. In the event of a write operation to an SRAM cell 12 in column k, write control signal WR[k] is driven active high, while write control signal WR[k] remains inactive low (no write is being performed to column k+1 in this example). The active high level on write control signal WR[k] turns off write assist transistor 17k, isolating power supply line Vddm[k] from power supply node Vdd. This floating state on power supply line Vddm[k] allows a low logic level on the desired one of bit lines BLk, BL*k to more easily flip the state of the SRAM cell 12 in the selected row of column k, as that low level bit line will not be “fighting” the high voltage bias from power supply node Vdd. Rather, the drive of the p-channel transistor 13p, 14p that has been maintaining the “1” level at its drain is weakened by the floating state on power supply line Vddm[k] in this write assist operation. Meanwhile, the voltage at power supply node Vdd remains biasing SRAM cells 12 in column k+1 since write assist transistor 17k+1 remains on; this maintains the previously latched data states in that column k+1.
FIG. 1d illustrates, by way of simulation, how this floating Vdd approach is effective in allowing “weak” SRAM cells to properly write a data state. In the timing diagram of FIG. 1d, during the time period between time t0 and time t1, write assist transistor 17k is turned off during a write operation to a weak (e.g., imbalanced) SRAM cell 12j,k; word line WLk is turned on during this operation, selecting row j. In this example, prior to time t0, SRAM cell 12j,k has latched a high level on node S1 and a low level on node S2; the write will attempt to flip that state to its opposite. As evident in the time period of the write, between time t0 and time t1, power supply line Vddm[k] is slightly discharged by the attempt to change the state of node S2 from low to high (by discharging node S1 to the low level of bit line BLk). The voltage at node S2 increases slightly as, in this case, transistor 14p is turned on by the low level on bit line BLk (via pass transistor 15a), but that voltage on node S2 does not reach a level sufficient to turn off cross-coupled transistor 13p in SRAM cell 12j,k. This inability to change the state of SRAM cell 12j,k is due to an imbalance in SRAM cell 12j,k that allows the voltage on power supply line Vddm[k] to overpower the low level on bit line BLk. Upon the end of this write period, at time t1, node S2 returns to its previously low level. The write has failed.
In this simulation of this conventional write assist approach, write assist transistor 17k is turned on during the write between time t2 and time t3, allowing power supply line Vddm[k] to float. The write is then attempted again by the low level at bit line BLk in combination with an active level on word line WLj, at time t2. In this case, because power supply line Vddm[k] is floating, the low level on bit line BLk is able to pull node S1 sufficiently low that transistor 14p turns on, charging node S2 to a high enough voltage that the state of SRAM cell 12j,k flips. At the end of the write operation at time t3, this new state of SRAM cell 12j,k is latched.
While this conventional write assist approach allows a weak cell to be written, as described above, it has been observed that this approach involves substantial power consumption. As evident from FIG. 1d, the voltage of power supply line Vddm[k] has been discharged substantially, on the order of 175 mV in this simulation example. This discharge similarly occurs on each column written, regardless of whether a weak bit is present. At the end of the assisted write, upon write assist transistors 17 again being turned on, each power supply line Vddm[k] is then charged back to its full power supply voltage Vdd, which of course consumes power in each write operation.
Another conventional write assist approach applies a reduced clamped voltage to the entire memory array block during writes to that memory array block, and also applies a reduced power supply voltage in a power-down mode. An example of this clamped approach is shown in FIG. 1e, in connection with memory array block 6m in which 6-T SRAM cells 12 are arranged in rows and columns, as described above. In this conventional approach, bias circuit 18m is associated with memory array block 6m, and derives a voltage on power supply line Vddm, which is connected to all SRAM cells 12 in memory array block 6m. As such, a single instance of bias circuit 18m is provided for each memory array block 6m, in contrast to the arrangement of FIG. 1c in which write assist transistors 17 are provided for individual columns.
In this example, bias circuit 18m includes p-channel MOS transistor 22 with its source at power supply voltage Vdd, and its gate receiving power down signal PD[m] for memory array block 6m. A complementary MOS (CMOS) inverter consists of p-channel MOS transistor 25p with its source connected to the drain of transistor 22, and its drain connected to the drain of n-channel MOS transistor 25n; the gates of transistors 25p, 25n are connected in common to receive write enable signal WE[m], which indicates that a write operation is to be performed to one or more SRAM cells 12 in memory array block 6m. A diode chain of p-channel MOS transistors 25d1, 25d2, with their source-drain paths connected in series between the source of n-channel transistor 25n and ground; transistors 25d1, 25d2 each has its gate connected to its drain, in diode fashion. Transistor 25d3 is also connected in diode fashion (gate connected to drain), with its source at power supply voltage Vdd and its drain and gate connected to the common drain node of transistors 25p, 25n, at power supply line Vddm.
In normal operation for read operations, both of control signals PD[m], WE[m] are inactive low. This turns on both of transistors 22 and 25p, and turns off transistor 25n; in this state, power supply line Vddm is at the full voltage of the Vdd power supply. In a power-down mode, control signal PD[m] is driven active high while control signal WE[m] remains inactive low. In this case, transistors 22 and 25n are both turned off, causing the voltage at power supply line Vddm to be at one diode threshold voltage below the Vdd power supply voltage, through the action of diode-connected transistor 25d3. As such, all of SRAM cells 12 in memory array block 6m are biased to this lower voltage Vad-Vt in this power-down mode.
Write assist is accomplished, in this conventional circuit arrangement, upon control signal WE[m] being driven active high for a write to one of SRAM cells 12 in memory array block 6m, while power-down control signal PD[m] remains inactive low. This turns off transistors 25p (and 22), allowing the voltage at power supply line Vddm to be pulled down toward ground through the series diode connection of 25d1, 25d2. The resulting voltage at power supply line Vddm will depend on the characteristics of diode-connected transistors 25d1, 25d2, 25d3, as well as the on resistance of transistor 25n. But it is contemplated that, in the steady-state, the voltage of power supply line Vddm will generally approach two threshold voltages above ground. As described above, all of SRAM cells 12 within memory array block 6m will receive this reduced power supply voltage during write operations.
Upon completion of the write operation using the conventional technique of FIG. 1e, power supply line Vddm must be charged back up to its full Vdd level. As a result, while this conventional arrangement assists in the writing of weak SRAM cells 12, by reducing the voltage against which the cross-coupled nodes are pulled low, substantial power is consumed by the repeated discharging and charging of power supply line Vddm for the entire memory array block 6m.